1. Field of the Invention
The present invention relates to a data transfer memory comprising a plurality of memory devices such as a plurality of dynamic random access memories (DRAMs) having the function of transferring data on one system bus within a bus system, or a plurality of memory modules each having such memory devices mounted therein.
Generally, for improving an efficiency of a whole bus system, various kinds of data items must be input or output at high speed between a plurality of memory devices or memory modules and a central processing unit (CPU).
The present invention relates to a data transfer memory device constructed by arranging a plurality of memory devices on a system bus or arranging a plurality of memory modules, each of which has the plurality of memory devices mounted therein, on the system bus. The present invention refers to a technique for continuously transferring various kinds of data items, which are an object of input or output from or to each memory device or memory module, at high speed over a bus line included in the system bus.
2. Description of the Related Art
For an easy understanding of problems underlying a data transfer memory of a prior art, a bus system employing the data transfer memory of the prior art will be described with reference to FIGS. 1 to 3 that will be described in xe2x80x9cBRIEF DESCRIPTION OF THE DRAWINGSxe2x80x9d.
FIG. 1 shows a configuration of a bus system according to the first example of the prior art. The bus system comprises a plurality of memory devices realized with a plurality of Rambus DRAMs that operate in a Rambus mode, or a plurality of memory modules each having the plurality of Rambus DRAMs mounted therein. Note that data transfer bus lines (normally referred to as DQ lines) included in a system bus 7 are omitted from the drawing.
Furthermore, referring to FIG. 1, one chip set (chip set #0) 40 realized with a CPU or the like, a reference signal generator 42, first to m-th memory devices or memory modules 100-1, 100-2, etc., and 100-m (hereinafter a plurality of memory devices or memory modules 100-1 to 100-m where m denotes any positive integer) are interconnected on a clock line included in the system bus 7. The clock line is turned back and used as a data output clock line for use in sending a clock from the plurality of memory devices or memory modules 100-1 to 100-m to the chip set 40, and a data input clock line for use in sending a clock from the chip set 40 to the plurality of memory devices or memory modules 100-1 to 100-m. 
Herein, a transfer clock T-CLK is transferred over the data output clock line, and a receive clock R-CLK is transferred over the data input clock line. In this case, the transfer clock T-CLK and receive clock R-CLK are transferred using the same clock line alone. It is thus prevented that data input to each memory-device or memory module and data output from each memory device or memory module become out of phase with each other. The level of a signal on the clock line is adjusted using a voltage supplied from a power supply Vt via a level adjustment resistor Rt1.
In the bus system of the first example of the prior art shown in FIG. 1, whichever of the plurality of memory devices that are Rambus DRAMs is accessed, data items output from the plurality of memory devices or memory modules to the chip set 40 have the same timing. However, when a signal delay time t dependent on a system bus length L or the length of bus lines constituting the system bus becomes equal or longer than a half of a data transfer time, the time from the moment when a protocol is input synchronously with the receive clock R-CLK until data is output synchronously with the transfer clock T-CLK becomes short. The upper limit of the system bus length L is therefore restricted. As a data transfer rate increases and becomes higher, the system bus length L must be made smaller.
On the other hand, the time necessary for an acknowledge packet to arrive at the chip set may be monitored. This enables the chip set to detect arrival of data in advance. However, the time necessary for the acknowledge packet to arrive at the chip set is determined by a distance from each memory device or memory module. The chip set must therefore wait for the time.
FIG. 2 shows a configuration of a bus system in accordance with the second example of the prior art. The bus system comprises a plurality of memory devices that operate in a DQ strobe mode, or a plurality of memory modules each having the memory devices mounted therein. Note that a DQ line included in a system bus 7 is omitted from the drawing.
Furthermore, referring to FIG. 2, bus lines constituting the system bus 7 include an MCLK line for use in transferring a main clock MCLK to be sent from one chip set 40 such as a CPU to first to m-th memory devices or memory modules 110-1, 110-2, etc., and 110-m (hereinafter a plurality of memory devices or memory modules 110-1 to 110-m), and a DQS line for use in transferring a DQ strobe DQS originated when data is output from any of the plurality of memory devices or memory modules 110-1 to 110-m. The level of a signal on the MCLK line is adjusted using a voltage supplied from a power supply Vt via a level adjustment resistor Rt2. The level of a signal on the DQS line is adjusted using a voltage supplied from the power supply Vt via another level adjustment resistor Rt3.
Furthermore, referring to FIG. 2, the chip set 40, reference signal generator 42, and plurality of memory. devices or memory modules 110-1 to 110-m are interconnected on the MCLK line and DQS line.
In the bus system of the second example of the prior art shown in FIG. 2, the plurality of memory devices or memory modules 110-1 to 110-m receive input data synchronously with the main clock MCLK. On the other hand, the plurality of memory devices or memory modules each output data synchronously with the DQ strobe DQS generated by the memory device or memory module during data output (that is, data reading).
Furthermore, according to another method, when data is input to the plurality of memory devices or memory modules (that is, during data writing), the chip set 40 controls a DQ strobe terminal. The plurality of memory devices or memory modules receives input data according to the timing of controlling the DQ strobe terminal.
According to this method, a signal delay time t dependent on a system bus length L arises. The time necessary for a memory device or memory module to receive a read instruction for instructing data reading, or the time necessary for the chip set 40 to receive data output from a memory device or memory module varies depending on the position of the memory device or memory module. In this case, a first access time necessary for the chip set 40 to receive data for the first time after the chip set 40 issues the read instruction cannot be controlled by the chip set 40. The chip set 40 must therefore change the position of a data reception window according to data output from a memory device or memory module.
In particular, the time required to receive data output from the first memory device or memory module 110-1 located closest to the chip set 40 differs greatly from the time required to receive data output from the m-th memory device or memory module 110-m located farthest from the chip set 40. Every time the chip set 40 receives data from any of the memory devices or memory modules, it must reset the position of the data reception window.
FIG. 3 shows a configuration of a bus system in accordance with the third example of the prior art. The bus system comprises a plurality of memory modules each having a plurality of memory devices, which operate in a return clock mode, mounted therein.
Furthermore, referring to FIG. 3, bus lines constituting a system bus 7 include an MCLK line for use in transferring a main clock MCLK, which is sent from a chip set 40 to first to m-th memory modules 120-1, 120-2, etc., and 120-m (hereinafter a plurality of memory modules 120-1 to 120-m), during data input, and an RCLK line for use in transferring a return clock RCLK, which is sent from the plurality of memory modules 120-1 to 120-m to the chip set 40, during data output. The level of a signal on the MCLK line is adjusted using a voltage supplied from a power supply Vt via a level adjustment resistor Rt4. The level of a signal on the RCLK line is adjusted using a voltage supplied from the power supply Vt via another level adjustment resistor Rt5.
Even in FIG. 3, like the first example of a prior art shown in FIG. 1, the one chip set 40 formed with a CPU or the like, reference signal generator 42, and plurality of memory modules 120-1 to 120-m are interconnected on the MCLK line, RCLK line, and DQ line included in the system bus 7.
However, in the bus system of the third example of the prior art shown in FIG. 3, unlike the first example of the prior art shown in FIG. 1, a module buffer composed of a delayed lock loop (DLL) 500 for adjusting the phase of a clock and a buffer amplifier 510 is included in each of the memory modules 120-1 to 120-m. Moreover, a power supply Vcc for supplying a voltage used to drive each semiconductor device in each memory module is connected to an enabling terminal EN of the memory module 120-m located farthest from the chip set 40 via a level adjustment resistor Rpm.
In this case, the module buffer in the memory module 120-m is activated according to the voltage level at the enabling terminal EN (herein, the level of a supply voltage supplied from the power supply Vcc) in response to the main clock MCLK transferred from the chip set 40. The thus activated module buffer receives the main clock MCLK, and causes the DLL 510 thereof to correct the phase of the main clock MCLK. The main clock MCLK is used as a clock for achieving synchronization of data output performed by the plurality of memory devices mounted in each memory module. In this case, therefore, the return clock RCLK is generated by the memory module instead of the transfer clock T-CLK employed in the first example of a prior art shown in FIG. 1. In the return clock mode, like the Rambus mode employed in the first example of a prior art, whichever of the memory modules is accessed, data output from an accessed memory module arrives at the chip set 40 according to the same timing.
However, even in the return clock mode, when a signal delay time t dependent on a system bus length L becomes equal to or longer than a half of a data transfer time, there arises a difference in access time between data in the memory module 120-1 located closest to the chip set 40 and data in the memory module 120-m located farthest therefrom in the same manner as in the Rambus mode adopted in the first example of a prior art.
As mentioned above, in the bus system of the first example of the prior art, as a signal delay time dependent on the length of bus lines constituting a system bus gets longer, the time for which a chip set must wait for data sent from a memory device located farthest from the chip set gets longer. It therefore becomes hard to transfer data at high speed. This poses a problem that an efficiency of the whole system deteriorates.
Furthermore, in the bus system of the second example of the prior art, when a signal delay time dependent on the length of bus lines constituting a system bus gets longer, the time necessary for a chip set to receive data output from a memory device or memory module differs among memory devices or memory modules. Accordingly, the position of a data reception window in the chip set must be changed according to the position of a memory device or memory module relative to the chip set. This poses a problem that an efficiency of the whole system deteriorates.
Furthermore, in the bus system of the third example of the prior art, when a signal delay time dependent on the length of bus lines constituting a system bus becomes equal to or longer than a half of a data transfer time, the time necessary for data in a memory module located closest to a chip set to arrive at the chip set, and the time necessary for data in a memory module located farthest therefrom to arrive at the chip set become mutually different like those in the first example of the prior art. Consequently, like the first example of the prior art, it becomes hard to transfer data at high speed. This poses a problem that an efficiency of the whole system deteriorates.
The present invention attempts to solve the foregoing problems. An object of the present invention is to provide a data transfer memory making it possible to transfer various kinds of data items continuously at high speed between a plurality of memory devices or memory modules and a CPU or the like, and to improve an efficiency of the whole system.
For solving the foregoing problems, according to the present invention, there is provided a data transfer memory comprising a plurality of memory devices that have the function of transferring data on one system bus and are controlled by a data processing unit for processing the data. The plurality of memory devices each comprise: a return clock input/output circuit for inputting or outputting a return clock generated using a clock output from the data processing unit; and an output activation circuit for activating output of the data in response to a data output enabling signal generated synchronously with the return clock output from the return clock input/output circuit.
Preferably, in the data transfer memory of the present invention comprising the plurality of memory devices, only a memory device located at a given position generates the return clock and data output enabling signal.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory devices, the memory device located at the given position is a memory device located farthest from the data processing unit on the system bus.
More preferably, in the data transfer memory of the present invention comprising the plurality of memory devices, the plurality of memory devices except the memory device located at the given position are selected to output data by means of the data processing unit, they receive as inputs the return clock and data output enabling signal generated by the memory device located at the given position. Output of the data is activated in response to the data output enabling signal. The data is output synchronously with the return clock.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory devices, when the memory device located at the given position is selected to output data by means of the data processing unit, output of the data is activated in response to a data output enabling signal generated by the memory device located at the given position. The data is output synchronously with a return clock generated by the memory device located at the given position.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory devices, the return clock and the data output enabling signal are each set to any phase. The adjustment of the phases of the return clock and data output enabling signal is carried out by a DLL or the like in each memory device.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory devices, an input circuit portion of the data processing unit and an input circuit portion of the output activation circuit in each memory device are activated only for a given time in response to the data output enabling signal.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory devices, a controller chip for outputting the return clock and the data output enabling signal is installed on the system bus.
According to the present invention, there may be provided a data transfer memory comprising a plurality of memory modules, in place of the plurality of memory devices described above. Herein, the plurality of memory modules each include a plurality of memory devices and a memory module buffer for use in inputting or outputting the data and various kinds of signals between the plurality of memory devices and the data processing unit.
Furthermore, the memory module buffer includes a return clock input/output circuit for inputting or outputting a return clock generated using a clock output from the data processing unit, and an output activation circuit for activating output of the data in response to the data output enabling signal generated using the return clock output from the return clock input/output circuit.
Preferably, in the data transfer memory of the present invention comprising the plurality of memory modules, only a memory module buffer in a memory module located at a given position on the system bus generates the return clock and data output enabling signal.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory modules, the memory module located at the given position is a memory module located farthest from the data processing unit on the system bus.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory modules, when a memory module buffer other than the memory module buffer located at the given position is selected for outputting data by means of the data processing unit, the return clock and data output enabling signal generated using the memory module buffer in the memory module located at the given position are received as inputs. The return clock and data output enabling signal are then supplied to memory devices in the memory module selected to output data.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory modules, when a memory device in a memory module other than the memory module located at the given position is selected to output data by means of the data processing unit, the data output enabling signal supplied from the memory module buffer in the memory module located at the given position is received as an input output of the data is activated in response to the data output enabling signal, and the data is transmitted to an associated memory module buffer synchronously with the return clock.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory modules, when a memory device mounted in the memory module located at the given position is selected to output data by the data processing unit, the return clock and data output enabling signal generated using the memory module buffer in the memory module located at the given position are received as inputs. Output of the data is activated in response to the data output enabling signal, and the data is transmitted to the memory module buffer in the memory module located at the given position synchronously with the return clock.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory modules, the return clock and data output enabling signal are each set to any phase. The adjustment of the phases of the return clock and data output enabling signal is carried out by a DLL or the like included in the memory module buffer.
Furthermore, preferably, in the data transfer memory of the present invention comprising the plurality of memory modules, an input circuit portion of the data processing unit and an input circuit portion of each memory module buffer are activated only for a given time in response to the data output enabling signal.
According to the data transfer memory of the present invention comprising a plurality of memory device or memory modules, a memory device or memory module located farthest from the data processing unit formed with a CPU or the like generates a return clock. The return clock is used to generate a data output enabling signal for activating an output circuit portion of any memory device or memory module. The data output enabling signal flows in the same direction as the return clock synchronously with the return clock. However large a system bus length may be, even when a data transfer rate is so high that a data transfer time becomes equal to or shorter than a signal delay time, data can be transferred from any memory device or memory module on the system bus to the data processing unit formed with a CPU or the like for the same access time.
Briefly, according to the present invention, various kinds of data items can be transferred continuously at high speed between a plurality of memory devices or memory modules and a CPU or the like. A data transfer rate in a bus system can be retained at a maximum rate, and an efficiency of the whole system can be improved.